1 S1C33L11 32-bit single chip microcomputer 32-bit s1c33000 risc core multiply accumulation built-in 16k-byte ram 10-bit adc built-in lcd controller built-in usb1.1 function controller built-in camera interface description the S1C33L11 is a seiko epson original 32-bit microcomputer that features high speed, low power consump- tion, and low-voltage operation. the S1C33L11 consists of an s1c33000 32-bit risc type cpu as its core, peripheral circuits including a bus control unit, dma controller, interrupt controller, timers, serial interface with fifo, a/d converter, lcd controller, camera interface, jpeg codec, usb1.1 function controller, mmc (spi mode) interface and smartmedia interface, and also ram. three oscillation circuits and two plls are also included, supporting advanced operation, power-saving operation, and high-performance realtime clock func- tions. the S1C33L11 is ideal for portable products that require high-speed data processing. especially it is suitable for the application processor embedded in cellular phones and pdas (personal data assistance). features cmos lsi 32-bit parallel processing ............. s1c33000 risc core main clock ....................................................... 50mhz (max., up to 33mhz external clock input) sub clock ........................................................ 32.768khz (typ., crystal) lcdc clock ..................................................... 55mhz (max.) usb clock ....................................................... 48mhz (typ.) instruction set .................................................. 16-bit fixed length, 105 instructions (mac instruction is included, 2 cycles) internal ram size ............................................ gen eral-purpose ram : 16k bytes vram : 128k bytes lcd controller ................................................. s1d13710 equivalent 8 to 18-bit color lcd interface supports md-tft, d-tfd and tft panels (up to 2 lcd panels) resolution : programmable (max. 176 240 pixels) color depths : a maximum of 64k colors can be simultaneously displayed using a 260k-color pallet (16-bpp mode). a maximum of 256 colors can be simultaneously displayed using a 260k-color pallet (8-bpp mode). swivel view (90/180/270-degree hardware rotation of display image), mirror display, picture-in-picture plus, overlay function clock ti mer ...................................................... 1 channel programmable ti mer ....................................... 8 bits 6 channels and 16 bits 6 channels watchdog tim er ............................................... realized with a 16-bit programmable timer serial interface ................................................ 4 channels clock synchronization type and asynchronization type are selectable. usable as an infrared ray (irda) interface. ch.0 is selectable between a built-in buffer type (a 4 bytes of receive-data buffer and a 2 bytes of transmit-data buffer) and no buffer type.
2 S1C33L11 camera inte rface ............................................ 1 channel hardware jpeg codec yuv data capture (yuv 4:2:2, 4:2:0), yuv to rgb converter hardware resizer with trimming mmc (spi m ode) interface ............................. 1 channel supports 1 to 16-bit serial data transfer in master mode. smartmedia interface ...................................... 1 channel allows direct connection of a smartmedia. usb1.1 function controller .............................. endpoint : ep0, epa, epb, epc, epd (4 channels) fifo : 1,024 bytes 10-bit a/d converter ........................................ su ccessive approximation type, 8 input channels high-speed dma ............................................. 4 channels intelligent dma ................................................ 128 channels i/o port ............................................................ input port : 13 bits i/o port : 51 bits interrupt contro ller ........................................... external interrupts : 10 types internal interrupts : 43 types external bus interface ..................................... 26-b it address bus, 16-bit data bus, 7 chip enable pins sram and burst rom may be connected directly. shipping form .................................................. pfbga-208pin supply voltage ................................................ c ore voltage : 1.65 to 1.95v (1.8 0.15v) i/o voltage : 2.70 to 3.30v (3.0 0.3v) i/o voltage for usb : 3.00 to 3.60v (3.3 0.3v) power consumption ........................................ sleep state : 18? typ. halt state : 24mw typ. (50mhz, lcdc and usb not included) run state : 50mw typ. ? 1 (50mhz, lcdc and usb not included) lcd controller - camera and lcd i/f : 22mw typ. (50mhz, v dd , lcdc block only) - camera, lcd i/f and jpeg : 60mw typ. (50mhz, v dd , lcdc block only) usb controller - idle state : 13mw typ. (v dd , usb block only) ? 1: the values of power consumption during execution were measured when a test program that consisted of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instruction was being continuously executed.
3 S1C33L11 block diagram v dd v ss v dde osc3 osc4 plls0 pllc osc5sel osc1 osc2 fosc1(p14/p60) vcp pllv dd pllv ss fpdat[17:0] fpframe fpline fpshift drdy #fpcs1 #fpcs2 fpsclk fpa0 fpso fpvin1 fpvin2 lcdv dd osc5 osc6 #dmareqx(k50, k51, k53, k54) #dmaackx(p32, p33, p04, p06) #dmaendx(p15, p16, p05, p07) ad0?(k60?7) #adtrg(k52) av dde k50?4 k60?7 #reset #nmi #x2spd ea10md[1:0] #busreq(p34) #busack(p35) #busget(p31) dsio dst[2:0](p10?2) dpco(p13) dclk(p14) tst burnin t8ufx(p10?3) sinx(p00, p04, p27, p33) soutx(p01, p05, p26, p16) #sclkx(p02, p06, p25, p15) #srdyx(p03, p07, p24, p32) fsin0(p00) fsout0(p01) #fsclk0(p02) #fsrdy0(p03) p00?7, p10?6 p20?7, p30?5 p40?7, p50?5 p60?3 #smwe(p34) #smre(p35) sdi(p34) sdo(p35) spiclk(p33) cm1dat[7:0] cm1vref cm1href cm1clkout cm1clkin cmstrout mtst scanen cnf2 gpio[3:0] S1C33L11 exclx(p10?3, p15, p16) tmx(p22?7) 16-bit programmable timer (6 ch.) a[25:18](p40?47), a[17:1], a0/#bsl d[15:0] #rd #wrl/#wr #wrh/#bsh #ce10ex #ce[9:4](p55?50) #wait(p30) #gaas(p21) #gard(p31) bclk(p60) usbdp usbdm usbvbus usbv dd s1c33000 interrupt controller prescaler/pll/ selector a/d converter (8 ch.) osc3 osc1/ pll lcdc (lcd i/f, camera i/f, jpeg codec) osc5 clock timer ram 16kb intelligent dma (128 ch.) high-speed dma (4 ch.) usb 1.1 interface 8-bit programmable timer (6 ch.) serial interface standard (4 ch.) serial interface built-in fifo (1 ch.) input port input port input port pull-up control i/o port smartmedia interface nancy accelerator mmc (spi mode) interface bus control unit cpu core fig. 1 S1C33L11 functional block diagram
S1C33L11 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2003, all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5117 epson electronic devices website document code: 404625402 first issue july, 2003 printed november, 2003 in japan l http://www.epsondevice.com n.c. fpdat11 fpdat9 fpdat8 fpdat6 fpdat3 fpdat0 drdy fpso cm1clkout cm1href lcdv dd cm1dat4 cm1dat2 cm1dat1 p16 (excl5/ #dmaend1/ sout3) n.c. 1 u t r p n m l k j h g f e d c b a fpdat16 fpdat12 fpdat13 v ss fpdat4 v ss #fpcs1 fpshift fpline v dd fpvin2 cm1vref cm1dat5 cm1dat3 cm1dat0 dst0 (p10/excl0/ t8uf0) dst2 (p12/excl2/ t8uf2) 2 fpdat17 fpdat15 fpdat14 fpdat10 fpdat5 fpdat1 #fpcs2 lcdv dd v ss cmstrout fpvin1 cm1dat7 v ss v dd dst1 (p11/excl1/ t8uf1) dclk (p14/fosc1) v ss 3 gpio0 cnf2 gpio1 lcdv dd fpdat7 fpdat2 fpframe fpsclk fpa0 v ss cm1clkin cm1dat6 v ss p15 (excl4/ #dmaend0/ #sclk3) v dde p34 (#busreq/ #ce6/#smwe/ sdi) p35 (#busack/ #smre/sdo) 4 gpio3 v dd p07 (#srdy1/ #dmaend3) gpio2 dsio dpco (p13/excl3/ t8uf3) p33 (#dmaack1/ sin3/spiclk) p31 (#busget/ #gard) 5 p05 (sout1/ #dmaend2) p03 (#srdy0/ #fsrdy0) p04 (sin1/ #dmaack2) p06 (#sclk1/ #dmaack3) v dd p32 (#dmaack0/ #srdy3) k65 (ad5) k67 (ad7) 6 p21 (#dwe/ #gaas) p01 (sout0/ fsout0) p20 (#drd) p02 (#sclk0/ #fsclk0) av dde k64 (ad4) k63 (ad3) k66 (ad6) 7 osc3 p00 (sin0/ fsin0) #reset p22 (tm0) v ss k61 (ad1) k60 (ad0) k62 (ad2) 8 osc4 v ss plls0 ea10md0 p30 (#wait/ #ce4&5) #hcas (p40/a25) #lcas (p41/a24) a22 (p43) 9 pllc ea10md1 p23 (tm1) #nmi a23 (p42) a21 (p44) v dd a19 (p46) 10 v dde v ss scanen p24 (tm2/#srdy2) a20 (p45) a18 (p47) v dde a15 11 osc2 p61 p26 (tm4/sout2) p25 (tm3/ #sclk2) a17 a16 a14 a13 12 osc1 v dd p27 (tm5/sin2) p62 a12 a11 a8 a6 13 pllv ss mtst tst k51 (#dmareq1) k54 (#dmareq3) #ce8 (#ras1/ #ce14/ #ras3/p54) #x2spd #ce4 (#ce11/ #ce11&12/ p50) #wrh (#bsh) d0 v dd v ss v dde a10 a9 v ss a5 14 vcp b urnin k50 (#dmareq0) k53 (#dmareq2) v dd #ce7 (#ras0/ #ce13/ #ras2/p53) v ss #ce6 (#ce7&8/p52) #rd d3 d4 d7 d13 a1 a7 a4 a3 15 pllv dd v ss usbv dd k52 (#adtrg) #ce10ex (#ce9&10ex) osc5sel p63 #ce5 (#ce15/ #ce15&16/ p51) #wrl (#wr/#we) v dde d1 d5 d9 d10 d15 a0 (#bsl) a2 16 n.c. usbdp usbdm usbvbus v dde #ce9 (#ce17/ #ce17&18/ p55) osc5 osc6 v dd bclk (p60/fosc1) d2 d6 d8 d11 d12 d14 n.c. 17 bold : the terminal (signal) name of a default setup. pin layout pfbga-208pin fig. 2 pin layout diagram (pfbga-208pin) top view bottom view index u t r p n m l k j h g f e d c b a u t r p n m l k j h g f e d c b a 12345678910111 21314151617 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a1 corner a1 corner
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